Senior hardware verification engineer with substantial experience in electronic product development, specializing in USB protocol implementation, SoC design, and embedded systems. Holds multiple U.S. patents related to security subsystems and communication protocols. Published author of comprehensive embedded eLearning curricula and recognized expert in FPGA/ASIC verification methodologies using UVM and SystemVerilog.

Career Highlights

  • Verification Engineer at a major medical device company—UVM verification and testbench development for next-generation medical devices, including ARM Cortex-M3 SWJ/JTAG debug interfaces and embedded communication protocols
  • Design and Verification Engineer at a leading aerospace research organization—Image processing and system integrity monitoring for advanced instrumentation systems using Xilinx and Microchip FPGA platforms
  • FPGA Design Engineer at a major cloud infrastructure company—Architected security subsystem for bare-metal computing infrastructure on Lattice MachX03 devices; issued U.S. patents for security architecture and secure communication protocols
  • Design and Verification Engineer at a semiconductor IP design firm—Led USB 3.x Device/Host controller IP development using SystemC/HLS, created DUT configuration randomization framework and UVM-SystemVerilog interfaces
  • SoC Verification roles at leading semiconductor and hardware companies including an AI/ML chip design company, a major semiconductor manufacturer, and a major aerospace and defense contractor—experience with AI/ML accelerator SoCs, wireless VR platforms with 802.11ad hardware, and controller IP integration
  • Systems Engineer at a networking infrastructure company and a leading semiconductor test equipment manufacturer—Developed SoC/FPGA specifications for high-speed USB 3.2 data transfer systems and supported advanced verification IP selection

Expert Qualifications

  • Recognized authority in USB 2.0/3.x protocol implementation, USB Chapter 9 enumeration, and device controller architecture with extensive hands-on hardware development experience
  • Patent-holder with demonstrated expertise in security subsystems, secure communication protocols, and embedded system architecture documented in issued U.S. patents
  • Extensive cross-disciplinary litigation readiness spanning medical device hardware, aerospace systems, consumer electronics, cloud infrastructure, and semiconductor IP development
  • Master of systematic documentation practices and cross-functional communication; skilled at assessing complex technical problems, providing rigorous solutions, and presenting findings to diverse audiences