Senior technology consultant with over two decades of expertise in semiconductor design, verification, and architecture. Specialized knowledge spans DDR SDRAM memory controller design, constrained random verification methodologies, and SoC integration across multiple leading companies in the semiconductor and networking sectors. Holds advanced degrees in computer science and engineering from top-tier universities, with extensive practical experience in RTL implementation, FPGA design verification, and HDL-level analysis for patent infringement determinations.

Formal Education

  • Master of Science in Computer Science from a leading research university
  • Bachelor of Science in Computer Engineering from a top-tier engineering university

Career Highlights

  • Principal Consultant at a silicon services consulting firm, specializing in ASIC/FPGA architecture, SoC verification, and memory controller design
  • Senior Member of Technical Staff at a high-performance computing company, leading high-throughput search indexer design and vectorized algorithm development on x86 processors
  • Senior Member of Technical Staff at a networking equipment company, developing network processor design and DDR SDRAM memory controller optimization for high-throughput applications
  • Senior Design Engineer on chipset design team at a leading semiconductor manufacturer, with responsibilities in RTL implementation, synthesis, and verification
  • Graduate Student Researcher at a leading research university on federally-funded research for optical interconnect systems

Expert Qualifications

  • Testified as expert witness in patent litigation addressing semiconductor design and verification methodologies
  • Served as consulting expert for multiple organizations in patent litigations and ITC investigations involving semiconductor architecture and mobile device design
  • Named inventor on nine U.S. patents in memory controller optimization, virtual address translation, and SoC design
  • Senior member of IEEE and ACM with peer-reviewed publications on FPGA synthesis, optical interconnects, and hardware design methodologies