Semiconductor packaging engineer with over 40 years of expertise in flip chip bumping, wafer-level packaging, and solder-based interconnect technologies. Recognized as a leading authority in IC assembly processes and advanced packaging design, with specialized knowledge in multi-chip module integration and chip scale packaging for semiconductor applications. Has provided extensive expert witness and consulting services to major semiconductor manufacturers and equipment suppliers. Holds 13 issued U.S. patents and 40+ peer-reviewed publications on packaging innovations and assembly technologies.
Formal Education
- Bachelor of Science in Mechanical Engineering from University of Wisconsin-Madison
- Master of Science in Manufacturing Systems from University of Wisconsin-Madison
Career Highlights
- Managing Partner of a specialized consulting firm providing expert witness services and consulting on IC packaging technologies from solder bumping through assembly
- VP Technology and CTO at a semiconductor equipment manufacturer, leading all R&D in flip chip bumping and WLP technologies and achieving significant market penetration
- VP and CTO at a semiconductor packaging technology company, directing all R&D in image sensor packaging and establishing comprehensive IP strategy
- Advisory Engineering Manager at a major semiconductor manufacturer, responsible for flip chip equipment and process engineering for multi-chip modules in computing systems
- Product Manager at a leading semiconductor equipment manufacturer, launching pioneering flip chip placement equipment to market
- Chair of a major industry technical working group and organizer of industry workshops; recipient of recognition awards from professional organizations
- Holds 13 issued U.S. patents covering flip chip, chip scale packaging, and assembly innovations, plus 40+ peer-reviewed publications
Expert Qualifications
- Testifying expert in multiple semiconductor packaging patent disputes; prepared expert reports and testified at trial
- Consulting expert in numerous semiconductor technology patent cases and disputes involving major industry participants
- Extensive background as consulting and testifying expert in multiple district court and ITC cases, plus numerous IPR proceedings, specializing in semiconductor packaging and IC assembly technologies
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Frequently Asked Questions
What types of cases can this expert support?
They've testified in semiconductor packaging patent disputes across district court, ITC, and IPR proceedings. Cases involving automotive electronics, mobile devices, optical equipment, and mechanical design are their wheelhouse. They handle patent disputes, reliability failures, and manufacturing process issues.
What is this expert's technical background?
BS in Mechanical Engineering, MS in Manufacturing Systems. Forty+ years in semiconductor packaging with VP/CTO roles, R&D leadership in flip chip and wafer-level technologies, and equipment engineering positions. Holds 13 patents and 40+ peer-reviewed publications.
What technologies does this expert specialize in?
Flip chip solder bumping, wafer-level packaging, chip scale packages, under bump metallization, and multi-chip modules. Also handles image sensor packaging, lead-free solder, solder joint reliability, thermal cycling, and electromigration analysis.
- Flip chip solder bumping
- Wafer-level packaging (WLP)
- Chip scale package (CSP) design
- Under bump metallization (UBM)
- Solder paste bumping processes
- Multi-chip module (MCM) assembly
- Image sensor packaging
- Lead-free solder processes
- Electromigration analysis
- Thermal cycling reliability
- U.S. District Courts
- Patent Trial and Appeal Board
- International Trade Commission