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race condition

1. n. A situation in which the combined effects of two or more programmatic threads (or a single thread and an ISR) varies depending on the precise order in which the instructions of each are executed.

Race conditions can be eliminated by surrounding critical code sections that must be executed without interruption with a pair of mutex take and release system calls. To prevent race conditions involving ISRs, interrupts must be disabled for the duration of the critical section.

EXAMPLE: If two threads both try to increment a shared global variable (x = x + 1;) and they race, the result of both threads incrementing the variable once from an initial value (x = 0;) can be either 2 (correct) or 1 (incorrect).

This race condition exists if either increment step is not executed atomically. If a context switch occurs in the middle of an increment (which is typically a sequence of three CPU instructions to read the old value into a register, increment the content of the register, then write the new value), an incorrect value can result. The error might not always occur, making tracking down such bugs incredibly difficult.

The outcome (final value of x) in this case is dependent on the precise order in which the instructions of the two threads are executed. The shared data and random nature of preemptive context switches are the culprits that cause the race condition.

2. n. A situation in digital logic where timing errors cause erratic outputs.

random access memory

n. A broad classification of memory devices that includes all devices in which individual memory locations can be read or written in any order required by the application. Abbreviated RAM. Misused to mean memory that can be both read and written, but the term is so broadly (mis)used in this fashion that nearly everyone assumes random access is the same as read-write. [more]

See also read-only memory.

rate monotonic analysis

n. The process of analyzing a real-time system to assign individual thread priorities according to the rate monotonic algorithm. [more]

read-only memory

n. A broad classification of memory devices that includes all devices in which memory locations cannot be modified. Abbreviated ROM. Misused to mean any nonvolatile memory, including flash and EEPROM, that can be modified in-system. [more]

See also random access memory.

real-time operating system

n. An operating system designed specifically for use in real-time systems. Abbreviated RTOS. [more]

real-time system

n. Any computer system, embedded or otherwise, that has timeliness requirements. The following question can be used to distinguish real-time systems from the rest: "Is a late answer as bad, or even worse, than a wrong answer?" In other words, what happens if the computation doesn't finish in time? If nothing bad happens, it's not a real-time system. If someone dies or the mission fails, it's generally considered "hard" real-time, which is meant to imply that the system has hard deadlines. Everything in between is "soft" real-time. [more]

EXAMPLE: Most industrial automation equipment has deadlines. If the bottle doesn't get a cap applied properly as it passes by on the production line, there is a failure. However, the consequences of that failure would not be as severe as the consequences of a failure in an airplane, a pacemaker, or any of a thousand other hard real-time systems.


adj. Said of software that calls itself. Recursion should generally be avoided in an embedded system, since it frequently requires a large stack.


adj. Said of software that can be executed multiple times simultaneously. A reentrant function can be safely called recursively or from multiple tasks. The key to making code reentrant is to ensure mutual exclusion whenever accessing global variables or shared registers. [more]


n. A memory-like location that is part of a processor or an I/O device. The reference to the register is encoded as part of the instruction, not as a discrete address. A processor register is much faster to read or write than a location in memory. Generally, each bit or set of bits within a peripheral register controls or tracks some behavior of the larger device.


n. A file containing object code that is almost ready for execution on the target. The final remaining step is to use a locator or loader to fix the remaining relocatable addresses within the code. The result of that process is an executable.

reset address

n. The address from which the first instruction will be fetched after a processor is powered on or reset; usually in ROM.

reset code

n. A small piece of code that is placed at the reset address. The reset code is usually written in assembly language and might simply be the equivalent of "jump to the startup code."

reset vector

See reset address.

resistance temperature detector

n. A temperature-sensitive wire, often made of copper, nickel, or platinum, that's used to measure temperature. Abbreviated RTD. An RTD can be constructed on a ceramic part. Common RTD materials are copper, platinum, or nickel. [more]

Compare to thermistor.


(as letters) 1. See rate monotonic algorithm.

2. See rate monotonic analysis.

ROM emulator

n. A debugging tool that plugs into the target system's ROM sockets (or that attaches to the SMT ROM parts). ROM emulators link the target system to a host computer. A plug either inserts into the target ROM sockets, clips over SMT ROM chips, or is soldered down in place of the ROM parts. The emulator then links this connection to the host computer over RS-232, Ethernet, or USB.

A ROM emulator lets the developer examine and change memory, I/O, and registers. It will support breakpoints (usually software-only), and single stepping. The biggest advantage of a ROM emulator is that it doesn't require a dedicated target comm port, as a ROM monitor would.

ROM emulator

A ROM emulator from TechTools

ROM monitor

See debug monitor.


A common abbreviation for real-time operating system.