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parallel processing

n. The capability to apply two or more processors to a single computation.


n. A piece of hardware other than the processor, usually an I/O device. A peripheral can reside within the same chip as the processor; in which case, it can be called an integrated or on-chip peripheral.

physical address

n. The address that is placed on the address bus when accessing a memory location or register.


(pick) 1. N. A member of any of several microcontroller families from Microchip, formally termed PICmicro microcontrollers.

HISTORY: Back in 1975, General Instruments needed a way to compensate for the poor I/O performance of its 16-bit CP1600 CPU. Their solution was to dedicate a simpler CPU called a Peripheral Interface Controller (PIC) to the task. Around 1985, Arizona Microchip Technology spun out of General Instruments to focus on the PIC business, which continues to thrive. More than 2 billion PICs had been sold by 2002.

(as letters) 2. abbr. Short for Position-Independent Code. See relocatable.


(rhymes with lid) 1. abbr. A three-part technique for designing control systems that use feedback. Short for Proportional–Integral–Derivative. The individual proportional (to the current error), integral (of all past errors), and derivative (predictor) terms work in conjunction to drive the system to its desired state quickly and with only minor overshoot.

PID controllers have been used for over a century in various mechanical, pneumatic, and electronic forms. A digital PID controller is implemented as firmware running on a processor. [more] [even more]

2. abbr. See process ID.


(as letters) abbr. See programmable logic device.


n. A method of interfacing to a peripheral that involves repeatedly reading a status register until the device has reached the awaited state. Device drivers are either polling or interrupt-driven, with the latter being more generally preferred.


adj. An operating system is said to be preemptive if it allows the running task to be suspended when a task of higher priority becomes ready (or a task of equal priority is granted a turn). Nonpreemptive schedulers are easier to implement but less appropriate for embedded systems, which must be responsive to external events. [more]


n. The relative urgency of one task or interrupt compared to another. In the case of tasks, the priority is an integer and the scheduler in a preemptive priority-based operating system compares the priorities of all that are ready to run and selects the one with the highest urgency to run.

priority inversion

n. An unwanted software situation in which a high-priority task is delayed while waiting for access to a shared resource that is not even being used at the time. For all practical purposes, the priority of this task has been lowered during the delay period. Priority inversion arises when a medium-priority task preempts a lower priority task using a shared resource on which the higher priority task is pending. If the higher priority task is otherwise ready to run, but a medium-priority task is currently running instead, a priority inversion is said to occur.

Anytime you use a mutex in a preemptive operating system environment, priority inversion is a possible result. A workaround, such as priority inheritance protocol, can be used to bound the length of this inversion but not eliminate it entirely. [more]


1. n. A word that is often confused with thread. The crucial distinction is that processes have their own private virtual memory spaces. One or more threads can run in the memory space of each process.

Processes are more common in multiuser systems than in embedded systems, where the added security and reliability outweigh the overhead costs.

See also task.

2. n. In the context of product development, a sequenced set of activities performed by a collaborating set of workers resulting in a coherent set of project artifacts, one of which is the desired system.


n. A generic term that does not distinguish between microprocessor, microcontroller, network processor, or digital signal processor.

processor family

n. A set of related processors, usually successive generations from the same manufacturer. For example, Intel's 80x86 family began with the 8086 and now includes the 80186, 286, 386, 486, Pentium, and many others. The later models in a family are typically backward-compatible with the ones that came before.


adj. Said of a piece of software that is independent of the processor on which it will be run. Most programs that can be written in a high-level language are processor independent.

Contrast with processor-specific.


adj. A piece of software that is highly dependent on the processor on which it will be run. Such code must usually be written in assembly language. Poor design can make a high-level language program very processor specific; careless assumptions about the size of longs and ints in C, for example, or explicit accesses to memory that create a particular endianness limit portability.

Contrast with processor-independent.


n. A software development tool that collects and reports execution statistics for your programs. These statistics include the number of calls to each subroutine and the total amount of time spent within each. This data can be used to learn which subroutines are the most critical and, therefore, demand the greatest code efficiency. Unfortunately, such technology is not often available in the remote debugging environment typical of embedded systems development.

program counter

See instruction pointer.

programmable logic device

n. An integrated circuit that can be used to implement a digital logic design in hardware. Abbreviated PLD. PLDs require far less board area, power, and wiring than several equivalent 7400-series TTL parts. And their internal structure can be reprogrammed if the logic later changes. For these reasons, inexpensive programmable logic devices like PLAs (programmable logic arrays), PALs (programmable array logic), and GALs (generic array logic) are commonly used for address decoding and other "glue" logic on circuit boards. PLDs are not as large or as flexible as FPGAs. [more]


(like the senior prom) abbr. A type of ROM that can be written (programmed) with a device programmer. Short for Programmable Read-Only Memory. These memory devices can be programmed only once, so they are sometimes referred to as write-once or one-time programmable. [more]

See also one-time programmable. Compare to EPROM.

protocol stack

n. Any set of communication protocols, such as TCP/IP, that consists of two or more layers of software and hardware. It's called a stack because each layer builds on the functionality in the layer below.

For example, in TCP/IP parlance, the lowest layer is called the physical layer. That's where the rubber meets the road; or, more accurately, the bits meet the communications medium at the network interface. Above that is the data link layer, which gives each device on the network its unique address. These first two layers of the TCP/IP protocol stack are typically implemented in hardware. Once the networked devices have addresses, they can communicate. That's where layer three, the network layer, comes in. IP is just one of the protocols that exists at this level in a TCP/IP stack; TCP and UDP are competing protocols at the transport layer.

Three more layers of software (session, presentation, and application) are defined above those, thus completing the seven-layer OSI reference model. When data is sent across the network, it generally begins at layer 4 or above, travels down through the protocol stack on the sending system, out onto the network, then back up the stack on the receiving system.

TCP/IP protocol stack

Some of the protocols in the TCP/IP protocol stack

pulse width modulation

n. A digital control technique wherein the processor adjusts the duty cycle of a sequence of fixed-width pulses. Abbreviated PWM. Unlike other modulation techniques, PWM is used more to control external analog signals or mechanical devices than to transmit data.

Consider driving a motor: a simple analog approach is to bias a transistor by varying amounts to control the motor's speed. This is very inefficient because the transistor dissipates considerable amounts of heat. PWM offers an alternative: connect the same transistor to a digital output pin and control the duty cycle of a train of pulses. Now the transistor is either on or off, so there's little power (P = I2 × R) loss.

Other applications abound. Passing the digital output through a lowpass filter converts the pulses to analog—the voltage a function of duty cycle. In effect, it's a cheap D/A converter.

Many processors have built-in PWM controllers that generate the pulse stream for a programmable duty cycle. [more]